메뉴 건너뛰기




Volumn , Issue , 2010, Pages 257-262

Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system

Author keywords

data cache; low power; write buffer

Indexed keywords

CACHE ARCHITECTURE; DATA CACHES; ENERGY CONSUMPTION; ENERGY REDUCTION; LOW POWER; ON-CHIP CACHE; READ OPERATION; RESOURCE-CONSTRAINED; TAG MATCHING; TOTAL ENERGY CONSUMPTION; WRITE OPERATIONS;

EID: 77954509589     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1785481.1785542     Document Type: Conference Paper
Times cited : (2)

References (17)
  • 2
    • 33646944134 scopus 로고    scopus 로고
    • A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors
    • T Ishihara, F Fallah, "A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors", In Proc. of the conference on Design, Automation and Test, 2005.
    • Proc. of the Conference on Design, Automation and Test, 2005
    • Ishihara, T.1    Fallah, F.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.