Efficient and scalable barrier synchronization for many-core CMPs

CF 2010 - Proceedings of the 2010 Computing Frontiers Conference

Volumn , Issue , 2010, Pages 73-74

  Abellán, José L ^a   Fernández, Juan ^a   Acacio, Manuel E ^a  

^a UNIVERSITY OF MURCIA   (Spain)

Author keywords

g line based barrier synchronization; global interconnection lines; many core cmps; s csma technique

Indexed keywords

4-CYCLE; BARRIER SYNCHRONIZATION; DATA NETWORK; INTERCONNECTION LINES; MANY-CORE; NETWORKS ON CHIPS; NOVEL HARDWARE; PERFORMANCE SIMULATOR; SOFTWARE-BASED;

SYNCHRONIZATION;

EID: 77954494246     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1787275.1787289     Document Type: Conference Paper

References (5)

1. http://www.netlib.org/benchmark/livermorec.
2. A. F. et al. Sim-powercmp: A detailed simulator for energy consumption analysis in future embedded cmp architectures. In AINA Workshops (1), pages 752-757, May 2007.
3. J. M. M.-C. et al. Synchronization without contention. In ASPLOS, pages 269-278, April 1991.
4. J. S. et al. Exploiting fine-grained data parallelism with chip multiprocessors and fast barriers. In MICRO, pages 235-246, December 2006.
5. T. K. et al. Noc with near-ideal express virtual channels using global-line communication. In Hot Interconnects, pages 11-20, August 2008.