A 200 μa duty-cycled PLL for wireless sensor nodes in 65 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 7, 2010, Pages 1305-1315

  Drago, Salvatore ^a   Leenaerts, Domine M W ^a   Nauta, Bram ^b   Sebastiano, Fabio ^a   Makinwa, Kofi A A ^c   Breems, Lucien J ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

^b UNIVERSITY OF TWENTE   (Netherlands)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

CMOS; duty cycle; frequency stability; frequency synthesizer; fully integrated; PLL; ultra low power; wireless sensor networks; WSN

Indexed keywords

CMOS; DUTY CYCLES; DUTY-CYCLE; FULLY INTEGRATED; ULTRA-LOW POWER;

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; FREQUENCY STABILITY; FREQUENCY SYNTHESIZERS; PHASE LOCKED LOOPS; SENSOR NETWORKS; SENSOR NODES; TELECOMMUNICATION EQUIPMENT;

WIRELESS SENSOR NETWORKS;

EID: 77954161705     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2049458     Document Type: Conference Paper

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