High-performance and low-voltage sense-amplifier techniques for sub-90nm SRAM

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 113-116

  Sinha, M ^a   Hsu, S ^b   Alvandpour, A ^b   Burleson, W ^a   Krishnamurthy, R ^b   Borkar, S ^b  

^a University of Massachusetts   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Capacitance; Charge transfer; CMOS technology; Delay; Differential amplifiers; Integrated circuit interconnections; Microprocessors; Operational amplifiers; Random access memory; Voltage

Indexed keywords

CAPACITANCE; CHARGE TRANSFER; CMOS INTEGRATED CIRCUITS; DIFFERENTIAL AMPLIFIERS; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT INTERCONNECTS; MICROPROCESSOR CHIPS; OPERATIONAL AMPLIFIERS; PROGRAMMABLE LOGIC CONTROLLERS; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE;

BITLINE CAPACITANCE; CMOS TECHNOLOGY; CURRENT SENSE AMPLIFIERS; DELAY; INTEGRATED CIRCUIT INTERCONNECTIONS; RANDOM ACCESS MEMORY; SENSING TECHNIQUES; SPEED IMPROVEMENT;

AMPLIFIERS (ELECTRONIC);

EID: 77954087785     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241474     Document Type: Conference Paper

References (9)

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