A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 5, 1998, Pages 793-798

  Kawashima, Shoichiro ^a,b,c,d,e   Mori, Toshihiko ^a,b,c,f,g   Sasagawa, Ryuhei ^a,b   Hamaminato, Makoto ^b   Wakayama, Shigetoshi ^b   Sukegawa, Kazuo ^b   Fukushi, Isao ^b  

^a IEEE   (Japan)

^b FUJITSU LABORATORIES LTD   (Japan)

^c Fujitsu Limited ^*

^d UNIVERSITY OF TOKYO   (Japan)

^e JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^f OSAKA UNIVERSITY   (Japan)

^g STANFORD UNIVERSITY   (United States)

Author keywords

Charge transfer amp; Encoded bus; Low power DLL; Low power SRAM

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRON DEVICE MANUFACTURE; ENERGY DISSIPATION; MOSFET DEVICES; SIGNAL ENCODING;

CHARGE TRANSFER AMPLIFIER; ENCODED BUS;

RANDOM ACCESS STORAGE;

EID: 0032075447     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.668995     Document Type: Article

References (13)

1. M. Izumikawa, H. Igura, K. Furuta, H. Ito, H. Wakabayashi, K. Nakajima, T. Mogami, T. Horiuch, and M. Yamashina, "A 0.25-μm CMOS 0.9-V 100-MHz DSP core," IEEE J. Solid-State Circuits, vol. 32, pp. 52-61, Jan. 1997
2. H. Shimada, S. Kawashima, H. Itoh, N. Suzuki, and T. Yabu, "A 46-ns 1-Mbit CMOS SRAM," IEEE J. Solid-State Circuits, vol. 23, pp. 53-58, Feb. 1988.
3. M. Yoshimoto, K. Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano, and T. Nakano, "A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM," IEEE J. Solid-State Circuits, vol. SC-18, pp. 479-484, Oct. 1983.
4. L. G. Heller, D. P. Spampinato, and Y. L. Yao, "High sensitivity chargetransfer sense amplifier," IEEE J. Solid-State Circuits, vol. SC-11, pp. 596-601, Oct. 1976.
5. E. Seevinck, P. J. van Beers, and H. Ontrop, "Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's," IEEE J. Solid-State Circuits, vol. 26, pp. 525-536, Apr. 1991.
6. M. Matsumiya, S. Kawashima, M. Sakata, M. Ookura, T. Miyabo, T. Koga, K. Itabashi, K. Mizutani, H. Shimada, and N. Suzuki, "A 15-ns 16-Mb CMOS SRAM with interdigitated bit-line architecture," IEEE J. Solid-State Circuits, vol. 27, pp. 1497-1503, Nov. 1992.
7. K. Sasaki, K. Ishibashi, K. Ueda, K. Komiyaji, T. Yamanaka, N. Hashimoto, H. Toyoshima, F. Kojima, and A. Shimizu, "A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier," IEEE J. Solid-State Circuits, vol. 27, pp. 1511-1518, Nov. 1992.
8. K. Seno, K. Knorpp, L.-L. Shu, N. Teshima, H. Kihara, H. Sato, F. Miyaji, M. Takeda, M. Sasaki, Y. Tomo, P. T. Chuang, and K. Kobayashi, "A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier," IEEE J. Solid-State Circuits, vol. 28, pp. 1119-1124, Nov. 1993.
9. K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimoto, N. Ohki, A. Shimizu, T. Hashimoto, T. Nagano, and T. Nishida, "A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers," IEEE J. Solid-State Circuits, vol. 30, pp. 480-486, Apr. 1995.
10. S. Yamamoto, N. Tanimura, K. Nagasawa, S. Meguro, T. Yasui, O. Minato, and T. Masuhara, "A 256K CMOS SRAM with variable impedance data-line loads," IEEE J. Solid-State Circuits, vol. SC-20, pp. 924-928, Oct. 1985.
11. M. Matsui, T. Ohtani, J. Tsujimoto, H. Iwai, A. Suzuki, K. Sato, M. Isobe, K. Hashimoto, M. Saitoh, H. Shibata, H. Sasaki, T. Matsuno, J. Matsunaga, and T. Iizuka, "A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines," IEEE J. Solid-State Circuits, vol. SC-22, pp. 733-740, Oct. 1987.
12. K. Ishibashi, "High-speed CMOS SRAM technologies for cashe applications," ICICE Trans. Elec., vol. E79-C, no. 6, pp. 724-734, June 1996.
13. M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, "A 1.5-ns 32-b CMOS ALU in double pass-transistor logic," IEEE J. Solid-State Circuits, vol. 28, pp. 1145-1151, Nov. 1993.