Novel test structures for temperature budget determination during wafer processing

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2010, Pages 30-33

  Faber, Erik J ^a   Wolters, Rob A M ^a,b   Schmitz, Jurriaan ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Metallization; Process monitoring; Silicon on insulator technology; Temperature measurement

Indexed keywords

4-POINT PROBE; ACTUAL TEMPERATURE; CRUCIAL PARAMETERS; LINE CONFIGURATION; METAL LAYER; METALLIZATION; METALLIZATION PROCESS; NOVEL METHODS; OPERATING RANGES; PLANAR TECHNOLOGY; PROCESSING STEPS; RESISTANCE MEASUREMENT; SI WAFER; SILICIDE FORMATION; TEMPERATURE BUDGET; TEMPERATURE HISTORY; TEMPERATURE INFORMATION; TEST STRUCTURE; WAFER PROCESSING;

METAL REFINING; METALLIZING; MICROELECTRONICS; PALLADIUM; PROCESS CONTROL; PROCESS MONITORING; SEMICONDUCTING SILICON COMPOUNDS; SILICIDES; SILICON; SILICON WAFERS; TEMPERATURE MEASUREMENT;

SILICON ON INSULATOR TECHNOLOGY;

EID: 77953905651     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.2010.5466867     Document Type: Conference Paper

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