A case for shared instruction cache on chip multiprocessors running OLTP

Proceedings of the 2003 Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '03

Volumn , Issue , 2003, Pages 11-18

  Kundu, Partha ^a   Annavaram, Murali ^a   Diep, Trung ^a   Shen, John ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH REQUIREMENT; CACHE MISS RATES; CACHE ORGANIZATION; CODE SEGMENTS; CODE STREAMS; INSTRUCTION CACHES; MISS-RATE; MULTIPLE PROCESSORS; ON CHIPS; ON-CHIP MULTIPROCESSOR; ORACLE DATABASE; SHARED CACHE; SPATIAL LOCALITY;

HYDRAULICS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY;

MICROPROCESSOR CHIPS;

EID: 77953591500     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1152923.1024297     Document Type: Conference Paper

References (13)

1. L.A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. In Proceedings of the 27th International Symposium on Computer Architecture, pages 282-293, June 2000.
2. K. Olukotun, B.A. Nayfeh, L. Hammond, K. Wilson and K. Chang. The Case for a Single-Chip Multiprocessor. In Proceedings of the 7th International Symposium on Architectural Support for Parallel Languages and Operating Systems, pages 2-11, October 1996.
3. A. Ailamaki, D. DeWitt, M. Hill, and D. Wood. DBMSs on a Modern Processor: Where Does Time Go? In Proceedings of the 25th International Conference on Very Large Data Bases, pages 266-277, September 1999.
4. K. Keeton, D.A. Patterson, Y.Q. He, R.C. Raphael, and W.E. Baker. Performance Characterization of a Quad Pentium Pro SMP Using OLTP Workloads. In Proceedings of the 25th International Symposium on Computer Architecture, pages 15-26, June 1998.
5. L.A Barroso, K. Gharachorloo, and E. Bugnion. Memory System Characterization of Commercial Workloads. In Proceedings of the 25th International Symposium on Computer Architecture, pages 3-14, June 1998.
6. P. Ranganathan and K. Gharachorloo and S.V. Adve and L.A. Barroso. Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors. In Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 307-318, October 1998.
7. N.P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. In Proceedings of the 17th International Symposium on Computer Architecture, pages 364-373, May 1990.
8. K.M. Wilson and K. Olukotun. Designing High-Bandwidth On-Chip Caches. In Proceedings of the 24th International Symposium on Computer Architecture, pages 121-132, June 1997.
9. Standard Performance Council. The SPEC95 CPU Benchmark Suite. http://www.spec.org/cpu2000
10. A.R. Alameldeen and D.A. Wood. Variability in Architectural Simulations of Multi-threaded Workload. In Proceedings of the 9th Annual International Symposium on High Performance Computer Architecture, pages 7-18, February 2003.
11. J. Lo, L. A. Barroso, S. Eggers, K. Gharachorloo, H. Levy, and S. Parekh. An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors. In Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 39-50 June 1998.
12. A. Ramirez, L. A. Barroso, K. A. Gharachorloo, R. Cohn, J. Larriba-Pey, P. G. Lowney, M. Valero. Code Layout Optimizations for Transaction Processing Workloads. In Proceedings of the 28 th Intl. Symposium on Computer Architecture, pages 155-164, June 2001.
13. P.S. Magnusson, F. Dahlgren, H. Grahn, M. Karlsson, F. Larsson, F. Lundholm, A. Moestedt, J. Nilsson, P. Stenström, and B. Werner. SimICS/sun4m: A Virtual Workstation. In Proceedings of the Usenix Annual Technical Conference, pages 119-130, June 1998.