Further investigation of EUV process sensitivities for wafer track processing

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7636, Issue , 2010, Pages

  Bradon, Neil ^a   Nafus, K ^b   Shite, H ^b   Kitano, J ^b   Kosugi, H ^b   Goethals, M ^c   Cheng, S ^c   Hermans, J ^c   Hendrickx, E ^c   Baudemprez, B ^c   Van Den Heuvel, D ^c  

^a Tokyo Electron Europe Limited   (United Kingdom)

^b TOKYO ELECTRON LTD   (Japan)

^c IMEC   (Belgium)

Author keywords

CD; Defectivity; EUV

Indexed keywords

CRITICAL DIMENSION UNIFORMITIES; CURRENT PROCESSING; CURRENT STATUS; DEFECTIVITY; FEATURE SIZES; MANUFACTURABLE PROCESS; PATTERNED WAFERS; POSTEXPOSURE BAKE; PROCESS DEFECTS; RESIST MATERIALS; ROADMAP; TOKYO ELECTRONS; TRACK PROCESSING;

DISSOLUTION; LITHOGRAPHY;

DATA STORAGE EQUIPMENT;

EID: 77953532706     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.846610     Document Type: Conference Paper

References (4)

1. Bradon, N., Weichert, H., Nafus, K., Hatakeyama, S., Kitano, J., Kosugi, H., Yoshihara, K., Goethals, M., Hermans, J. "Investigation of EUV-process sensitivities for wafer-track processing" Proc. SPIE 7271-48(2009).
2. Hermans, J., Baudemprez, B., Lorusso G., Hendrickx, E., Ronse, K., IMEC "Performance of the ASML EUV alpha demo tool" Proc. SPIE 7636-57 (2010) Manuscript submitted for publication.
3. Gronheid, R., Rathsack, B., Scheer, S., Nafus, K., Shite, H., Kitano, J. "EUV-RLS performance tradeoffs for a polymer bound PAG resist" Proc. SPIE 7639-21 (2010) Manuscript submitted for publication.
4. Shimoaoki, T., Enomoto, M., Nafus, K., Marumoto, H., Kosugi, H., Mallmann J., Maas, R., Verspaget, C., van der Heijden E., Wang, S. "Evaluation of next generation hardware for lithography processing" Proc. SPIE 7639-89 (2010) Manuscript submitted for publication.