Accurate Timed RTOS Model for Transaction Level Modeling

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 1333-1336

  Hwang, Yonghyun ^a   Schirner, Gunar ^b   Abdi, Samar ^c   Gajski, Daniel G ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NORTHEASTERN UNIVERSITY   (United States)

^c Dept of Electrical and Computer Engineering   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATE ESTIMATION; AT-SPEED; BEHAVIOR MODEL; C CODES; CONTEXT SWITCH; DYNAMIC SCHEDULING; INTERPROCESS COMMUNICATION; INTERRUPT HANDLING; JPEG ENCODERS; KEY FEATURE; MULTI CORE; ON-BOARD MEASUREMENTS; SYSTEM LEVEL DESIGN LANGUAGES; TRANSACTION LEVEL MODELING; TRANSACTION LEVEL MODELS;

DESIGN; DISPENSERS; MICROPROCESSOR CHIPS;

MATHEMATICAL MODELS;

EID: 77953105756     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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