Pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1998, Pages 93-96

  Wang, Jinn Shyan ^a   Yang, Po Hui ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY UTILIZATION; FIR FILTERS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; PIPELINE PROCESSING SYSTEMS; TIMING CIRCUITS; VLSI CIRCUITS;

PULSE-TRIGGERED TRUE-SINGLE-PHASE CLOCKING FLIP FLOPS (PTTFF);

FLIP FLOP CIRCUITS;

EID: 0031618669     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)