An optimized simulation-based fault injection and test vector generation using VHDL to calculate fault coverage

Proceedings - International Workshop on Microprocessor Test and Verification

Volumn , Issue , 2009, Pages 55-60

  Moazzeni, Shadi ^a   Poormozaffari, Saadat ^a   Emami, Amin ^b  

^a AMIRKABIR UNIVERSITY OF TECHNOLOGY   (Iran)

^b ISLAMIC AZAD UNIVERSITY   (Iran)

Author keywords

Fault coverage; Fault equivalence; Fault injection; Stuck at fault; Test vector generation

Indexed keywords

COMBINATIONAL LOGIC CIRCUITS; FAULT COVERAGES; FAULT EQUIVALENCE; FAULT INJECTION; FAULT MODEL; GATE MODELS; OPTIMIZED ALGORITHMS; OPTIMIZED SIMULATION; STUCK-AT FAULTS; TEST VECTORS;

LOGIC CIRCUITS; OPTIMIZATION; SWITCHING CIRCUITS; TESTING;

MICROPROCESSOR CHIPS;

EID: 77953036192     PISSN: 15504093     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTV.2009.22     Document Type: Conference Paper

References (14)

1. N. Nicola and B. M. Al-Hashimi. Power-Constrained Testing of VLSI Circuits . Kluwer Academic Publishers, 2003.
2. M. Nicolaidis, "Design for Soft-Errors Robustness to Rescue Deep Submicron Scaling," Panel in IEEE International Test Conf., 1998, pag. 1140
3. J. Clark, D. Pradhan, Fault Injection: A method for Validating Computer-System Dependability, IEEE Computer, June 1995, pp. 47-56
4. R. K. Iyer and D. Tang, Experimental Analysis of Computer System Dependability, Chapter 5 of Fault- Tolerant Computer System Design, D. K. Pradhan (ed.), Prentice Hall, 1996
5. M.C. Hsueh, T. Tsai, R.K. Iyer, Fault Injection Techniques and Tools, IEEE Computer, April 1997, pp. 75-82
6. E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, J. Karlsson, Fault injection into VHDL Models: the MEFISTO Tool, Proc. FTCS-24, Austin (USA), 1994, pp. 66-75
7. T.A. Delong, B.W. Johnson, J.A. Profeta III, A Fault Injection Technique for VHDL Behavioral-Level Models, IEEE Design & Test of Computers, Winter 1996, pp. 24-33
8. G.A. Kanawati, N.A. Kanawati, J.A. Abraham, FERRARI: A Flexible Software-Based Fault and Error Injection System, IEEE Trans. on Computers, Vol 44, N. 2, February 1995, pp. 248-260
9. J. Carreira, H. Madeira, J. Silva, Xception: Software Fault Injection and Monitoring in Processor Functional Units, DCCA-5, Conference on Dependable Computing for Critical Applications, Urbana-Champaign, USA, September 1995, pp. 135-149
10. S. Han, K.G. Shin, H.A. Rosenberg, Doctor: An Integrated Software Fault-Injection Environment for Distributed Real-Time Systems, Proc. IEEE Int. Computer Performance and Dependability Symposium, 1995, pp. 204-213
11. A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, "A Fault Injection Environment for Microprocessor-based Boards," IEEE International Test Conf., 1998, pp. 768-773
12. J. Karlsson, P. Liden, P. Dahlgren, R. Johansson, U. Gunneflo, Using Heavy-Ion Radiation to Validate Fault-Handling Mechanisms, IEEE Micro, Vol. 14, No. 1, pp. 8-32, 1994
13. R. Guo, I. Pomeranz, and S. M. Reddy, "Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits based on Vector Restoration," in Proc.of the Design Automation and Test in Europe Conf., Feb. 1998, pp. 583-587.
14. J. M. Galey, R. E. Norby, and J. P. Roth, "Techniques for the Diagnosis of Switching Circuit Failures," in R. S. Ledley, editor, Proc. of the Second Annual Symp. On Switching Circuit Theory and Logical Design, (Detroit), AIEE, Oct. 1961, pp. 152-160.