Thermally robust phosphorous nitride interface passivation for InGaAs self-aligned gate-first n-MOSFET integrated with high-k dielectric

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Oh, H J ^a   Lin, J Q ^a   Suleiman, S A B ^a   Lo, G Q ^b   Kwong, D L ^b   Chi, D Z ^c   Lee, S J ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATIVE ANALYSIS; EFFECTIVE MOBILITIES; GATE STACKS; HIGH-K DIELECTRIC; INTERFACE PASSIVATION; METAL GATE STACK; MOCVD; MOSFETS; NMOSFET; PASSIVATION LAYER; SELF-ALIGNED GATE; SUBTHRESHOLD SLOPE; SURFACE PASSIVATION; THERMAL STABILITY;

CHEMICAL VAPOR DEPOSITION; ELECTRON DEVICES; LOGIC GATES; MOSFET DEVICES; NITRIDES; PHOSPHORUS; PLASMA DEPOSITION; SEMICONDUCTING INDIUM; THERMODYNAMIC STABILITY; THERMOGRAVIMETRIC ANALYSIS;

PASSIVATION;

EID: 77952376525     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424354     Document Type: Conference Paper

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