A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (φ-Flash), suitable for full 3D integration

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Hubert, A ^a   Nowak, E ^a   Tachi, K ^a   Maffini Alvaro, V ^a   Vizioz, C ^a   Arvet, C ^a,c   Colonna, J P ^a   J M Hartmann, J M ^a   Loup, V ^a   Baud, L ^a   Pauliac, S ^a   Delaye, V ^a   Carabasse, C ^a   Molas, G ^a   Ghibaudo, G ^b   De Salvo, B ^a   Faynot, O ^a   Ernst, T ^a  

^a CEA LETI   (France)

^b IMEP LAHC   (France)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 4-LEVEL; CRYSTALLINE NANOWIRES; DOUBLE GATE; EXPERIMENTAL STUDIES; GATE-ALL-AROUND; MEMORY ARCHITECTURE; MEMORY ARRAY; MULTI-BITS; PROGRAMMING WINDOW; SONOS MEMORY;

CRYSTALLINE MATERIALS; ELECTRON DEVICES; NANOWIRES; THREE DIMENSIONAL;

FLASH MEMORY;

EID: 77952359666     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424260     Document Type: Conference Paper

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