Data processing on FPGAs

Proceedings of the VLDB Endowment

Volumn 2, Issue 1, 2009, Pages 910-921

  Mueller, Rene ^a   Teubner, Jens ^a   Alonso, Gustavo ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DATA HANDLING; PROGRAM PROCESSORS;

COMPUTATION MODEL; DESIGN CONSTRAINTS; GENERAL PURPOSE CPUS; HETEROGENEOUS MANY CORES; INTEGRATION STRATEGY; PARALLEL STREAMS; PROCESSING UNITS; SORTING NETWORK;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77952261145     PISSN: None     EISSN: 21508097     Source Type: Conference Proceeding    
DOI: 10.14778/1687627.1687730     Document Type: Article

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