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Volumn , Issue , 2005, Pages

Accelerating database operators using a network processor

Author keywords

[No Author keywords available]

Indexed keywords

CHIP AREAS; CLOCK RATE; DATA-BASE MANAGEMENT SYSTEMS; DATABASE OPERATORS; GENERAL PURPOSE PROCESSORS; HARDWARE ARCHITECTURE; HARDWARE SUPPORTS; INSTRUCTION LEVEL PARALLELISM; MEMORY ACCESS; MEMORY ACCESS LATENCY; MULTI CORE; MULTIPLE THREADS; MULTITHREADED; NETWORK PROCESSOR; OUT-OF-ORDER EXECUTION; OUT-OF-ORDER PROCESSORS; PROCESSOR CORES; SIMULTANEOUS MULTI-THREADING;

EID: 77953982164     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1114252.1114260     Document Type: Conference Paper
Times cited : (29)

References (22)
  • 9
    • 0034501522 scopus 로고    scopus 로고
    • Making pointer-based data structures cache conscious
    • T. M. Chilimbi, M. D. Hill, and J. R. Larus. Making pointer-based data structures cache conscious. IEEE Computer, 33(12):67-74, 2000.
    • (2000) IEEE Computer , vol.33 , Issue.12 , pp. 67-74
    • Chilimbi, T.M.1    Hill, M.D.2    Larus, J.R.3
  • 16
    • 65749311706 scopus 로고
    • Application of hash to data base machine and its architecture
    • M. Kitsuregawa, H. Tanaka, and T. Moto-Oka. Application of hash to data base machine and its architecture. New Generation Comput., 1(1):63-74, 1983.
    • (1983) New Generation Comput. , vol.1 , Issue.1 , pp. 63-74
    • Kitsuregawa, M.1    Tanaka, H.2    Moto-Oka, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.