A 90nm CMOS DSP MLSD transceiver with integrated AFE for electronic dispersion compensation of multi-made optical fibers at 10Gb/s

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 232-234

  Agazzi, Oscar ^a,b   Crivelli, Diego ^b   Hueda, Mario ^b   Carrer, Hugo ^b   Luna, Germán ^b   Nazemi, Ali ^a   Grace, Carl ^a   Kobeissy, Bilal ^a   Abidin, Cindra ^a   Kazemi, Mohammad ^a   Kargar, Mahyar ^a   Marquez, César ^a   Ramprasad, Sumant ^a   Bollo, Federico ^b   Posse, Vladimir ^a   Wang, Stephen ^a   Asmanis, Georgios ^a   Eaton, George ^a   Swenson, Norman ^a   Lindsay, Tom ^a   Voois, Paul ^a   more..

^a ClariPhy Communications Inc   (United States)

^b CLARIPHY ARGENTINA S A   (Argentina)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; DISPERSION COMPENSATION; OPTICAL FIBERS; TRANSCEIVERS;

10 GB/ S; 90-NM CMOS; ELECTRONIC DISPERSION COMPENSATION; LINE-CARD APPLICATIONS; MULTIMODES; PARALLEL PROCESSING;

OPTICAL TRANSCEIVERS;

EID: 49549113845     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523142     Document Type: Conference Paper

References (6)

1. IEEE Standard Association, IEEE Standard 802.3AQ-2006, Physical Layer and Management Parameters for 10Gb/s Operation, Type 10GBASE LRM, Sept. 15, 2006. Accessed on Nov. 12, 2007,
2. W.Rosenkranz and C.Xia, "Advanced Electronic Equalization for High Speed Data Transmission over Multi-Mode as well as Single-Mode Optical Fiber," Proc. European Conf. on Optical Communications (ECOC), Sept. 2005.
3. H. Bae J. B. Ashbrook, J. Park, et al., "An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links," ISSCC Dig. Tech. Papers, pp.234-235, Feb.2006.
4. IEEE LAN/MAN Standards Committee, "Gen 67 FDDI Monte Carlo Data Set," IEEE 802.3aq Task Force, Oct. 2004, Accessed on Nov. 12, 2007,
5. M. Harwood, N. Warke, R. Simpson, et al., "A 12.5Gb/s SerDes in 65nm CMOS Using a Baud Rate ADC with Digital Receiver Equalization and Clock Recovery," ISSCC Dig. Tech. Papers, pp.436-437, Feb. 2007.
6. G. Luna, D. Crivelli, M. Hueda, and O. Agazzi, "Compensation of Track and Hold Frequency Response Mismatches in Interleaved Arrays of Analog to Digital Converters for High-Speed Communications Receivers," Proc. IEEE ISCAS, pp.1631-1634, May 2006.