A 3.2GHz-sample-rate 800MHz bandwidth highly reconfigurable analog FIR filter in 45nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 90-91

  O'Hannaidh, Eoin ^a,b   Rouat, Emmanuel ^a   Verhaeren, Sarah ^a   Tual, Stéphane Le ^a   Garnier, Christophe ^a  

^a STMICROELECTRONICS   (France)

^b ST Ericsson   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG PERFORMANCE; CMOS TRANSISTORS; DEEP-SUBMICRON CMOS TECHNOLOGY; FAST SWITCHING; HARD DISK DRIVE; HIGH-ORDER; HIGH-SPEED; POWER SUPPLY; RE-CONFIGURABLE; RECONFIGURABILITY; WIRELESS VIDEO;

BANDWIDTH; FIR FILTERS; HARD DISK STORAGE; MICROPROCESSOR CHIPS;

CMOS INTEGRATED CIRCUITS;

EID: 77952118618     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5434034     Document Type: Conference Paper

References (7)

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4. P. Schvan et al., "A 24GS/s 6b ADC in 90nm CMOS", ISSCC Dig. Tech. Papers, pp. 544-545, Feb., 2008.
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7. F. Hussien et al., "Design Considerations for LPF with Gain Boosting in GHz-range Applications", IEEE MWSCAS, pp. 1107-1110 vol.2, Aug., 2005.