Low temperature plasma-enhanced ALD enables cost-effective Spacer Defined Double Patterning (SDDP)

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7520, Issue , 2009, Pages

  Beynet, Julien ^a   Wong, Patrick ^b   Miller, Andy ^b   Locorotondo, Sabrina ^b   Vangoidsenhoven, Diziana ^b   Yoon, Tae Ho ^c   Demand, Marc ^b   Park, Hyung Sang ^c   Vandeweyer, Tom ^b   Sprey, Hessel ^a   Yoo, Yong Min ^c   Maenhoudt, Mireille ^b  

^a ASM   (Belgium)

^b IMEC   (Belgium)

^c ASM   (South Korea)

Author keywords

Conformality; Critical Dimension Uniformity (CDU); Direct Spacer Defined Double Patterning (D SDDP); Line Width Roughness (LWR); Photoresist compatibility; Plasma Enhanced Atomic Layer Deposition (PEALD); Polysilicon gate patterning; Uniformity

Indexed keywords

CONFORMALITY; CRITICAL DIMENSION UNIFORMITIES; DOUBLE PATTERNING; LINE WIDTH ROUGHNESS (LWR); LINEWIDTH ROUGHNESS; PLASMA-ENHANCED ATOMIC LAYER DEPOSITION; POLYSILICON GATES;

ATOMIC LAYER DEPOSITION; ATOMS; CHEMICAL VAPOR DEPOSITION; COST REDUCTION; DEPOSITION; PLASMA DEPOSITION; PLASMAS; POLYSILICON; SEMICONDUCTING ORGANIC COMPOUNDS; SILICON COMPOUNDS; SILICON OXIDES; SILICON WAFERS;

ROUGHNESS MEASUREMENT;

EID: 77952086522     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.836979     Document Type: Conference Paper

References (4)

1. C. Bencher, Y. Chen, H. Dai, W. Montgomery, L. Huli, "22nm Half-Pitch Patterning by CVD Spacer Self Alignment Double Patterning (SADP)", Proceedings of SPIE, 6924 (2008).
2. Y.J. Kim, T.H. Yoon, J.S. Kim, J.H. Kim, H.Y. Kwon, Y.H. Kim, D.Y. Kim, H.S. Park, Y.M. Yoo, "Characterization of silicon oxide processed by PEALD", 8th International Conference on Atomic Layer Deposition (2008).
3. J. Finders, M. Dusa, B. Vleeming, H. Megens, B. Hepp, M. Maenhoudt, S. Cheng, T. Vandeweyer, "Double patterning for 32nm and below: an update", Proceedings of SPIE, 6924 (2008).
4. nd international workshop on Plasma Etch and Strip in Microlectronics (2009).