Rise time reduction of high speed digital signals on interconnects of the CMOS 45 nm node by optimizing interconnect inductance

SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference Proceedings

Volumn , Issue , 2009, Pages 407-411

  De Rivaz, S ^a   Lacrevaz, T ^a   Bermond, C ^a   Flechet B ^a   Farcy, A ^b  

^a UNIVERSITÉ DE SAVOIE   (France)

^b STMICROELECTRONICS   (France)

Author keywords

45 nm node; High frequency; High speed signals; Inductance; Interconnect; Propagation delay; Rise time

Indexed keywords

45NM NODE; HIGH FREQUENCY; HIGH-SPEED SIGNALS; PROPAGATION DELAYS; RISETIMES;

MICROWAVES; NANOTECHNOLOGY; OPTIMIZATION; SPEED;

INDUCTANCE;

EID: 77951716203     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMOC.2009.5427556     Document Type: Conference Paper

References (6)

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