A multi-bit cascaded sigma-delta modulator with an oversampled single-bit DAC

2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009

Volumn , Issue , 2009, Pages 49-52

  Kashmiri, Mahdi ^a   Makinwa, Kofi ^a   Breems, Lucien ^b  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; CASCADED SIGMA-DELTA MODULATOR; CONTINUOUS TIME; DYNAMIC ELEMENT MATCHING; LOOP DELAY; MULTI-BITS; OVERSAMPLED; QUANTIZERS; SAMPLING RATES; SINGLE-BIT;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DELTA MODULATION; DIGITAL INTEGRATED CIRCUITS; LINEARIZATION; MODULATION;

MODULATORS;

EID: 77951474162     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2009.5410950     Document Type: Conference Paper

References (6)

1. L.J. Breems, R. Rutten, G. Wetzker, "A cascaded continuous-time ΣΔ modulator with 67-dB dynamic range in 10-MHz bandwidth," IEEE J. Solid-State Circuits, vol.39, pp.2152-2160, Dec. 2004.
2. S.R. Northworty, R. Schrier, G.C. Ternes, "Delta-Sigma Data Converters, Theory, Design, and Simulation", IEEE Press, 1997, ISBN: 0-7803-1045.
3. L.R. Carley, "A noise-shaping coder topology for 15+ bit converters", IEEE J. Sold-State Circuits, vol.24, pp.267-273, Apr. 1989.
4. R.T. Baird, T.S. Fiez, "Linearity enhancement of multibit ΣΔ A/D and D/A converters using data weighted averaging", IEEE Transactions on Circ. and Syst. II: Express Briefs, vol.42, pp.753-762, Dec. 1995.
5. M. Sarhang-Nejad,G.C. Temes, "A high-resolution multibit ΣΔ ADC with digital correction and relaxed amplifier requirements", IEEE J. of Solid-State Circuits, vol.28, pp. 648-660, June 1993.
6. L.J. Breems, R. Rutten, R.H.M. van Veldhoven, G. van der Weide, "A 56mW continuous-time quadrature cascaded ΣΔ modulator with 77 dB DR in a near zero-IF 20 MHz band", IEEE J. of Solid-State Circuits, vol.42, pp. 2696-2705, Dec. 2007.