Evaluatin. The performance of a configurable, extensible VLIW processor in FFT execution

2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009

Volumn , Issue , 2009, Pages 771-774

  Stevens, D ^a   Glynn, N ^a   Galiatsatos, P ^b   Chouliaras, V ^a   Reisis, D ^b  

^a LOUGHBOROUGH UNIVERSITY   (United Kingdom)

^b UNIVERSITY OF ATHENS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

C CODES; COMPILER OPTIMIZATIONS; CONFIGURABLE; CPU CONFIGURATION; CUSTOM INSTRUCTION; CYCLE COUNT; CYCLE PERFORMANCE; DATA PATHS; DELAY FEEDBACK; FFT ALGORITHM; INLINING; LOOP UNROLLING; POWER DISSIPATION; RESOURCE MIX; SILICON AREA; VLIW PROCESSOR;

FAST FOURIER TRANSFORMS; NANOTECHNOLOGY; VERY LONG INSTRUCTION WORD ARCHITECTURE;

PROGRAM COMPILERS;

EID: 77951436479     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2009.5410773     Document Type: Conference Paper

References (8)

1. S. Leibson, J. Kim, "Configurable processors: a new era in chip design" IEEE Computer, July 2005, vol.38, no.7, pp. 51-59
2. V. A. Chouliaras, K. Koutsomyti, T. Jacobs, S. Parr, D. Mulvaney and R. Thomson, "SystemC-defined SIMD insttuctions for high performance SoC architectures" Proceedings oy the 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France, Dec 10 - 13, 2006
3. Gonzalez, R.E., "Xtensa: a configurable and extensible processor" Micro, IEEE Volume20, Issue 2, Mar/Apr 2000 Page(s):60 - 70
4. Clark D. Thompson "Fourier Transform in VLSI," IEEE Transactions on Computers, 1983.
5. R. M. Jiang, "An Area-Efficient FFT Architecture for OFDM Digital Video Broadcasting," IEEE Transactions on Consumer Electronics, Vol.53, No.4, November 2007.
6. S. He and M. Torkelson "Design and Implementation of a 1024-point Pipeline FFT Processor," IEEE 1998 Custom Integrated Circuits.
7. S. He and M. Torkelson "A New Approach to Pipeline FFT Processor" Proceedings oy the IPPS, 1996.
8. K. Manolopoulos, K. Nakos, D. Reisis, N.Vlassopoulos, V.A. Chouliaras "High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architecture" ICECS, December 2007.