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Volumn , Issue , 1997, Pages 260-271
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From algorithm parallelism to instruction-level parallelism: An encode-decode chain using prefix-sum
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Author keywords
[No Author keywords available]
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Indexed keywords
BANDWIDTH;
CODES (SYMBOLS);
COMPUTER PROGRAMMING LANGUAGES;
DATA STORAGE EQUIPMENT;
DECODING;
ENCODING (SYMBOLS);
KNOWLEDGE BASED SYSTEMS;
PARALLEL PROCESSING SYSTEMS;
PROGRAM COMPILERS;
REDUCED INSTRUCTION SET COMPUTING;
COMPLETENESS THEOREM;
INSTRUCTION LEVEL PARALLELISM (ILP);
PARALLEL PREFIX SUM (PS) FUNCTIONAL UNITS;
SERIAL PROGRAMMING LANGUAGES;
PARALLEL ALGORITHMS;
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EID: 0030719226
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (6)
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References (0)
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