Impact of cache coherence protocols on the processing of network traffic

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 161-171

  Kumar, Amit ^a   Huggahalli, Ram ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COHERENT LIGHT; COMPUTER ARCHITECTURE; INTERNET; NETWORK PROTOCOLS; STANDARDS; SYSTEMS ENGINEERING; TELECOMMUNICATION;

CACHE ACCESSES; CACHE COHERENCE PROTOCOLS; CACHE PLACEMENT; COHERENCE PROTOCOLS; GENERAL PURPOSE PROCESSOR (GPP); INBOUND NETWORK; INTERNATIONAL SYMPOSIUM; LOW-COMPLEXITY; MICRO ARCHITECTURES; NETWORK PERFORMANCES; NETWORK PROCESSING; NETWORK TRAFFICS; PREFETCH; PROTOTYPE IMPLEMENTATIONS; SPEED UPS;

NETWORK ARCHITECTURE;

EID: 47349093234     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.22     Document Type: Conference Paper

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