A third-order continuous-time sigma-delta modulator for bluetooth

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Volumn , Issue , 2009, Pages 247-250

  Yang, Wen Lin ^a   Hsieh, Wen Hung ^a   Hung, Chung Chih ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE-RC; BLUETOOTH APPLICATION; CHIP AREAS; CLOCK-JITTER; CMOS PROCESSS; CONTINUOUS TIME; CONTINUOUS-TIME SIGMA-DELTA MODULATORS; DIGITAL-TO-ANALOG CONVERTERS; DISTRIBUTED FEEDBACK; DYNAMIC RANGE; MEASUREMENT RESULTS; NON-RETURN-TO-ZERO; SIGMA-DELTA; SIGNAL BANDWIDTH; SINGLE-BIT; THIRD-ORDER;

BLUETOOTH; CMOS INTEGRATED CIRCUITS; COMPUTERIZED TOMOGRAPHY; CONTINUOUS TIME SYSTEMS; DESIGN; HYBRID COMPUTERS; JITTER; MODULATION; RAILROAD TUNNELS;

MODULATORS;

EID: 77950647951     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2009.5158141     Document Type: Conference Paper

References (7)

1. A. R. Feldman, B. Boser, and P. R. Gray, "A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications," IEEE J. Solid-State Circuits, vol. 33, pp. 1462-1469, Oct. 1998.
2. J. Grilo, I. Galton, K. Wang, and R. G., Montemayor, "A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver, "IEEE J. Solid-State Circuits, vol. 37, pp.271-278, Mar. 2002.
3. J. H. Nielsen and E. Bruun, "A Design Methodology For Power-Efficient Continuous-Time A/D Converters, "Proc. ISCAS. 2003, vol. 1, pp. 1069-1072, May, 2003.
4. L. J. Breems, "A Cascaded Continuous-Time ΔΣ Modulator with 67dB Dynamic Range in 10MHz Bandwidth," ISSCC Dig. Tech. Papers, pp. 72-73, Feb., 2004.
5. R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, Piscataway NJ: IEEE Press, 2005.
6. S. Yan and E. Sanchez-Sinencio, "A continuous-time sigmadelta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth," IEEE J. Solid-State Circuits, vol. 39, no.1, pp.75-86, Jan. 2004.
7. J. Morizio, et al., "14-bit 2.2-MS/s Sigma-Delta ADC's," IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 968-76, Jul. 2000.