Minimizing pattern effects resulting from rapid thermal processing

MICRO

Volumn 20, Issue 7, 2002, Pages 71-76

  Stancavate, Peter ^a  

^a AXCELIS TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 77950641511     PISSN: 10810595     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

1. P Vandenabeele and K Maes, "Temperature Nonuniformities during Rapid Thermal Processing of Patterned Wafers, " in Rapid Isothermal Processing Proceedings of SPIE 1189 (Belling-ham, WA: The International Society for Optical Engineering (SPIE), 1989), 89.
2. J Hebb and K Jensen, "Pattern Induced Temperature Non-Uniformity during Rapid Thermal Processing, " in Proceedings of the 4th International Conference on Advanced Thermal Processing of Semiconductors, RTP 1996 (New York, NY: IEEE, 1996).
3. The International Technology Roadmap for Semiconductors (San Jose: Semiconductor Industry Association, 2001).
4. PJ Timans, Z Nenyei, and R Berger, "Device Scaling Drives Pattern Effect Solutions, " Solid State Technology 45, no. 5 (2002): 67-72.
5. Z Nenyei, A Gschwandtner, and S Marcus, "How to Manage the Pattern Challenge, " in Proceedings of the 3rd International Rapid Thermal Processing Conference, RTP 1995 (New York, NY: IEEE, 1995), 58.
6. R Berger et al., "Pattern Shift Reduction in Dual Side Heated RTP Systems with Hot Shielding Technology, " in Proceedings of the 9th International Conference on Advanced Thermal Processing of Semiconductors, RTP 2001 (New York, NY: IEEE, 2001), 71.