Runtime temporal partitioning assembly to reduce FPGA reconfiguration time

ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs

Volumn , Issue , 2009, Pages 374-379

  Jara Berrocal, Abelardo ^a   Gordon Ross, Ann ^a  

^a University of Florida   (United States)

Author keywords

Field programmable gate arrays; Module placement; Partial reconfiguration; Temporal partitioning

Indexed keywords

DESIGN METHODOLOGY; FPGA FABRIC; HARDWARE MODULES; MODULE PLACEMENT; PARTIAL RECONFIGURATION; RE-CONFIGURABLE; RECONFIGURATION OVERHEAD; RECONFIGURATION TIME; RUNTIMES; TEMPORAL PARTITIONING; TIME MULTIPLEXING;

FABRICS; LOGIC GATES; MULTIPLEXING; SIMULATED ANNEALING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77950485536     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReConFig.2009.61     Document Type: Conference Paper

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