MultiGate SOI MOSFETs: Accumulation-mode vs. enhancement-mode

IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Volumn , Issue , 2008, Pages

  Afzalian, A ^a   Lederer, D ^a   Lee, C W ^a   Yan, R ^a   Xiong, W ^b   Rinn Cleavelin, C ^b   Colinge, J P ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCUMULATION MODES; CURRENT DRIVES; ENHANCEMENT-MODE; EXPERIMENTAL DATA; MULTI-GATE FETS; PROCESS VARIABILITY; SOI-MOSFETS;

MESFET DEVICES;

NANOELECTRONICS;

EID: 77949925420     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SNW.2008.5418482     Document Type: Conference Paper

References (8)

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3. S. Datta, Superlattices and Microstructures, Vol. 28 (4), 2000, pp. 253-278
4. L. Chang et al., IEEE TED, 2004, Vol.51 (10), pp. 1621-1627
5. W. Xiong et al., Abstracts of NATO International Advanced Research Workshop, "Nanoscaled Semiconductor-on-lnsulator Structures and Devices", 2006, pp. 95-96.
6. J.P. Colinge et al., Proc. Intl. SOI Conf, 1993, pp. 146-147.
7. J.P. Colinge, IEEE TED, Vol. 37 (3) 1990, pp. 718-723
8. W. Cheng et al., Jpn. J. Appl. Phys., Vol. 45 (4B), 2006, pp. 3110-3116