Design of a configurable fixed-point multiplier for digital signal processor

1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009

Volumn , Issue , 2009, Pages 217-220

  Zhang, Xinyue ^a   Li, Zhaolin ^a   Zheng, Qingwei ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; CONFIGURABLE; CRITICAL PATH DELAYS; MULTIPLICATION OPERATIONS; POINT MULTIPLIERS; PRODUCT OPERATIONS; VERILOG HDL;

CMOS INTEGRATED CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; MICROELECTRONICS; SIGNAL PROCESSING;

DIGITAL SIGNAL PROCESSORS;

EID: 77949606472     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRIMEASIA.2009.5397407     Document Type: Conference Paper

References (5)

1. Shiann-Rong Kuang and Jiun-Ping Wang, "Design of power-efficient configurable Booth multiplier," Circuits and Systems, in press.
2. Zhou Shun, Oliver A. Pḟander†, Hans-J̈org Pfleiderer† and Amine Berrnak, "A VLSI architecture for a run-time multi-precision reconfigurable Booth multiplier," 14th IEEE International Conference on Electronics, Circuits and Systems, pp. 975-978, December 2007.
3. Yan Sun, Lanfei Dong, Daheng Yue, Shaoqing Li, and Minxuan Zhang, "Multiple-precision subword-parallel multiplier using correction-value merging technique," 7th International Conference on ASIC, pp. 48-51, October 2007.
4. Dimitri Tan, Albert Danysh and Michael Liebelt, "Multiple-precision fixed-point vector multiply-accumulator using shared segmentation," 16th IEEE Symposium on Computer Arithmetic, pp. 12-19, June 2003.
5. Shankar Krithivasan and Michael J. Schulte, "Multiplier architectures for media processing," Conference Record of the Thirty-Seventh Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 2193-2197, November 2003.