Nano-CMOS circuit design and performance evaluation by inclusion of ballistic transport processes

2009 International Semiconductor Device Research Symposium, ISDRS '09

Volumn , Issue , 2009, Pages

  Chek, Desmond C Y ^a   Tan, Michael L P ^a,b   Arora, Vijay K ^a,c  

^a UNIVERSITI TEKNOLOGI MALAYSIA   (Malaysia)

^b UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^c WILKES UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 77949361761     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2009.5378261     Document Type: Conference Paper

References (5)

1. V.K. Arora, "Ballistic Quantum Transport in Nano Devices and Circuits," in 2nd IEEE International Nanoelectronics Conference, Shanghai, People's Republic of China, pp. 573-578, 2008
2. V.K. Arora, M.L.P. Tan, I. Saad, and R. Ismail, "Ballistic quantum transport in a nanoscale metal-oxide-semiconductor field effect transistor," Appl. Phy. Lett., vol. 91, pp. 103510 (3 pages), Sep 2007.
3. J. Łusakowski, W. Knap, Y. Meziani, J.-P. Cesso, A. El Fatimy, G. Ghibaudo, F. Boeuf and T. Skotnicki, "Ballistic and pocket limitations of mobility in nanometer Si metal-oxide semiconductor field-effect transistors," Appl. Phys. Lett., vol. 87, pp. 053507 (3 pages), July 2005.
4. A. Rothwarf, "A New Quantum Mechanical Channel Mobility Model for Si MOSFET's," IEEE Electron Device Letters, vol. EDL-8, no. 10, pp. 499-502, 1987.
5. V. Chan, R. Rengarajan, N. Rovedo, J. Wei, T. Hook, P. Nguyen, C. Jia, E. Nowak, C. Xiang-Dong, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C. Baiocco, P. Shafer, N. Hung, H. Shih-Fen, and C. Wann, "High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering," IEEE International Electron Devices Meeting 2003, Washington, DC, pp. 3.8.1-3.8.4, 2003.