Error control coding for multilevel cell flash memories using nonbinary low-density parity-check codes

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2009, Pages 367-375

  Maeda, Yuu ^a   Kaneko, Haruhiko ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BCH CODE; ERROR CHARACTERISTICS; ERROR CONTROL CODE; ERROR CONTROL CODING; ERROR PROBABILITIES; HAMMING CODE; HIGH-DENSITY; IRREGULAR LDPC CODES; LDPC CODES; LOW-DENSITY PARITY-CHECK CODES; MATRIX; MULTI-LEVEL CELL FLASH MEMORY; MULTILEVEL CELL FLASHES; NON-BINARY; NON-BINARY CODES; NON-BINARY LDPC CODES;

BIT ERROR RATE; CODING ERRORS; COMMUNICATION SYSTEMS; DEFECTS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; FLASH MEMORY; MEDIUM ACCESS CONTROL; PROBABILITY; PROBABILITY DENSITY FUNCTION; QUALITY ASSURANCE; TAPE DRIVES;

CODES (SYMBOLS);

EID: 77649280683     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2009.25     Document Type: Conference Paper

References (11)

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