Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit

Proceedings - IEEE Real-Time and Embedded Technology and Applications Symposium

Volumn 10, Issue , 2004, Pages 404-412

  Šůcha, Přemysl ^a   Pohl, Zdeněk ^b   Hanzálek, Zdeněk ^a  

^a CZECH TECHNICAL UNIVERSITY IN PRAGUE   (Czech Republic)

^b INSTITUTE OF INFORMATION THEORY AND AUTOMATION   (Czech Republic)

Author keywords

Cyclic scheduling; FPGA; Integer linear programming; Iterative algorithms; Monoprocessor

Indexed keywords

CYCLIC SCHEDULING; INTEGER LINEAR PROGRAMMING (ILP); ITERATIVE ALGORITHMS; MONOPROCESSORS;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; LINEAR PROGRAMMING; MATHEMATICAL MODELS; PROBLEM SOLVING; RAPID PROTOTYPING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 7744244024     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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