High performance self-aligned inversion-channel MOSFETs with In o.53Gao.47As channel and ALD-Al2O3 gate dielectric

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 2009, Pages 83-84

  Chiu, H C ^a   Chang, P ^a   Huang, M L ^a   Lin, T D ^a   Chang, Y H ^a   Huang, J C ^b   Chen, S Z ^b   Kwo, J W ^c   Tsai, W ^d   Honga, M ^a  

^a Dept of Matls Sci and Eng ^*  (Taiwan)

^b Matls Sci and Microsys   (Taiwan)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^d INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER DEPOSITED; BI-LAYER; CMOS LOGIC; DEVICE PERFORMANCE; GATE LENGTH; HIGH BREAKDOWN FIELDS; HIGH POTENTIAL; HIGH-SPEED; INVERSION CHANNELS; LOW POWER; MAXIMUM DRAIN CURRENT; MOS-FET; MOSFETS; NMOSFET; SELF-ALIGNED; WIDE BAND GAP;

ALUMINUM; DIELECTRIC RELAXATION; DRAIN CURRENT; GADOLINIUM; GALLIUM; GATE DIELECTRICS; GATES (TRANSISTOR);

MOSFET DEVICES;

EID: 76549106006     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2009.5354850     Document Type: Conference Paper

References (4)

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3. Y. Xuan, et al, IEDM 2008, p. 371.
4. H C. Chiu et al, Appl. Phys. Lett., V. 93, p. 202903 (2008).