-
1
-
-
76349119901
-
-
C. Barrett and C. Tinelli. CVC3. In CAV'07, 2007.
-
C. Barrett and C. Tinelli. CVC3. In CAV'07, 2007.
-
-
-
-
2
-
-
0031618668
-
A Decision Procedure for Bit-Vector Arithmetic
-
C. W. Barrett, D. L. Dill, and J. R. Levitt. A Decision Procedure for Bit-Vector Arithmetic. In DAC, pages 522-527, 1998.
-
(1998)
DAC
, pp. 522-527
-
-
Barrett, C.W.1
Dill, D.L.2
Levitt, J.R.3
-
4
-
-
72949103106
-
Deciding Fixed and Non-fixed Size Bit-vectors
-
N. Bjørner and M. C. Pichora. Deciding Fixed and Non-fixed Size Bit-vectors. In TACAS, pages 376-392, 1998.
-
(1998)
TACAS
, pp. 376-392
-
-
Bjørner, N.1
Pichora, M.C.2
-
5
-
-
76349126172
-
A Lazy and Layered SMT(BV) Solver for Hard Industrial Verification Problems
-
R. Bruttomesso, A. Cimatti, A. Franzen, A. Griggio, Z. Hanna, A. Nadel, A. Palti, and R. Sebastiani. A Lazy and Layered SMT(BV) Solver for Hard Industrial Verification Problems. In CAV, pages 247-260, 2007.
-
(2007)
CAV
, pp. 247-260
-
-
Bruttomesso, R.1
Cimatti, A.2
Franzen, A.3
Griggio, A.4
Hanna, Z.5
Nadel, A.6
Palti, A.7
Sebastiani, R.8
-
6
-
-
76349110776
-
-
Roberto Bruttomesso. RTL Verification: from SAT to SMT(BV). PhD thesis, University of Trento, 2008. Available at http://www.inf.unisi.ch/ postdoc/bruttomesso/files/phdthesis.pdf.
-
Roberto Bruttomesso. RTL Verification: from SAT to SMT(BV). PhD thesis, University of Trento, 2008. Available at http://www.inf.unisi.ch/ postdoc/bruttomesso/files/phdthesis.pdf.
-
-
-
-
7
-
-
76349087132
-
-
R. E. Bryant, S. K. Lahiri, and S. A. Seshia. Modeling and Verifying Systems using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions. In CAV, 2002.
-
R. E. Bryant, S. K. Lahiri, and S. A. Seshia. Modeling and Verifying Systems using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions. In CAV, 2002.
-
-
-
-
8
-
-
33748557565
-
An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
-
D. Cyrluk, M. O. Möller, and H. Rueß. An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors. In CAV, pages 60-71, 1997.
-
(1997)
CAV
, pp. 60-71
-
-
Cyrluk, D.1
Möller, M.O.2
Rueß, H.3
-
9
-
-
45749085681
-
Z3: An Efficient SMT Solver
-
L. de Moura and N. Bjørner. Z3: An Efficient SMT Solver. In TACAS'08, pages 337-340, 2008.
-
(2008)
TACAS'08
, pp. 337-340
-
-
de Moura, L.1
Bjørner, N.2
-
10
-
-
24944448541
-
Simplify: A theorem prover for program checking
-
D. Detlefs, G. Nelson, and J. B. Saxe. Simplify: a theorem prover for program checking. Journal of ACM, 52(3):365-473, 2005.
-
(2005)
Journal of ACM
, vol.52
, Issue.3
, pp. 365-473
-
-
Detlefs, D.1
Nelson, G.2
Saxe, J.B.3
-
12
-
-
26944496164
-
A Decision Procedure for Fixed-Width Bit-Vectors
-
Technical report, University of Stanford, Available at
-
V. Ganesh, S. Berezin, and D. L. Dill. A Decision Procedure for Fixed-Width Bit-Vectors. Technical report, University of Stanford, 2005. Available at http://theory.stanford.edu/~vganesh/ bitvector-tech-report.ps.
-
(2005)
-
-
Ganesh, V.1
Berezin, S.2
Dill, D.L.3
-
13
-
-
38149088089
-
A Decision Procedure for Bit-Vectors and Arrays
-
V. Ganesh and D. L. Dill. A Decision Procedure for Bit-Vectors and Arrays. In CAV, pages 519-531, 2007.
-
(2007)
CAV
, pp. 519-531
-
-
Ganesh, V.1
Dill, D.L.2
-
14
-
-
76349101422
-
Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic
-
S. Jha, R. Limaye, and S. A. Seshia. Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic. In CAV, 2009.
-
(2009)
In CAV
-
-
Jha, S.1
Limaye, R.2
Seshia, S.A.3
-
15
-
-
0000789133
-
The expected linearity of a simple equivalence algorithm
-
June
-
D. E. Knuth and A. Schönhage. The expected linearity of a simple equivalence algorithm. Theoretical Computer Science, 3(6):281-315, June 1978.
-
(1978)
Theoretical Computer Science
, vol.3
, Issue.6
, pp. 281-315
-
-
Knuth, D.E.1
Schönhage, A.2
-
16
-
-
38149078029
-
-
P. Manolios, S. K. Srinivasan, and D. Vroon. BAT: The Bit-Level Analysis Tool. In CAV, pages 303-306, 2007.
-
P. Manolios, S. K. Srinivasan, and D. Vroon. BAT: The Bit-Level Analysis Tool. In CAV, pages 303-306, 2007.
-
-
-
-
17
-
-
24944515509
-
Proof-Producing Congruence Closure
-
R. Nieuwenhuis and A. Oliveras. Proof-Producing Congruence Closure. In RTA'05, pages 453-468, 2005.
-
(2005)
RTA'05
, pp. 453-468
-
-
Nieuwenhuis, R.1
Oliveras, A.2
-
18
-
-
79957107478
-
-
to Verilog. Available at
-
Peter M. Nyasulu. Introduction to Verilog. Available at http://www.doe.carleton.ca/~shams/ 97350/PetervrlK.pdf.
-
Introduction
-
-
Nyasulu, P.M.1
-
19
-
-
76349113130
-
-
OpenSMT
-
OpenSMT. http://verify.inf.unisi.ch/opensmt.
-
-
-
-
20
-
-
48949101163
-
Lazy Satisfiability Modulo Theories
-
R. Sebastiani. Lazy Satisfiability Modulo Theories. JSAT, 3:144-224, 2007.
-
(2007)
JSAT
, vol.3
, pp. 144-224
-
-
Sebastiani, R.1
-
21
-
-
76349102564
-
-
Spear. http://www.cs.ubc.ca/~babic/.
-
Spear
-
-
-
22
-
-
0016495233
-
Efficiency of a good but not linear set union algorithm
-
R. E. Tarjan. Efficiency of a good but not linear set union algorithm. J. ACM, 22(2):215-225, 1975.
-
(1975)
J. ACM
, vol.22
, Issue.2
, pp. 215-225
-
-
Tarjan, R.E.1
-
23
-
-
49749135618
-
SWORD: A SAT like prover using word level information
-
R. Wille, G. Fey, D. Große, S. Eggersglüß, and R. Drechsler. SWORD: A SAT like prover using word level information. In VLSI-SoC, pages 88-93, 2007.
-
(2007)
VLSI-SoC
, pp. 88-93
-
-
Wille, R.1
Fey, G.2
Große, D.3
Eggersglüß, S.4
Drechsler, R.5
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