Design of a pipelined and expandable sorting architecture with simple control scheme

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  Lin, Chi Sheng ^a   Liu, Bin Da ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; NUMERICAL METHODS; VLSI CIRCUITS;

COMPARE-WAP CELL; DIGITAL SIGNAL PROCESSORS; INTERCONNECTION COMPACTNESS;

DIGITAL SIGNAL PROCESSING;

EID: 0036287330     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. An optimal hardware-algorithm for sorting using a fixed-size parallel sorting device
2. Minimizing communication in the bitonic sort
3. Realization of large-scale distributions based on batchers sorters
4. Efficient VLSI architecture for columnsort
5. Data-driven control scheme for linear array: Application to a stable insertion sorter
6. High-speed media filter designs using shiftable cotent-addressable memory
7. On balancing sorting on a linear array
8. A 512 16-b Bit-serial sorter chip
9. A generalized block distribution algorithm for fast carry-skip adder design