An optimal hardware-algorithm for sorting using a fixed-size parallel sorting device

IEEE Transactions on Computers

Volumn 49, Issue 12, 2000, Pages 1310-1324

  Olariu, Stephan ^a,b   Pinotti, M Cristina ^a,c   Zheng, Si Qing ^a,d  

^a IEEE   (Italy)

^b Old Dominion University   (United States)

^c UNIVERSITY OF TRENTO   (Italy)

^d The University of Texas at Dallas   (United States)

Author keywords

Columnsort; Hardware algorithms; Sorting networks; Special purpose architectures; VLSI

Indexed keywords

ALGORITHMS; DATA STORAGE EQUIPMENT; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; SORTING; TIME SHARING SYSTEMS; VLSI CIRCUITS;

BATCHER CLASSIC BITONIC SORTING NETWORK; OPTIMAL HARDWARE ALGORITHM; PARALLEL SORTING DEVICE;

COMPUTER HARDWARE;

EID: 0034514897     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.895849     Document Type: Article

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