Error-correcting codes for ternary content addressable memories

IEEE Transactions on Computers

Volumn 58, Issue 2, 2009, Pages 275-279

  Krishnan, Sriram C ^a   Panigrahy, Rina ^b   Parthasarathy, Sunil ^a  

^a CISCO SYSTEMS   (United States)

^b MICROSOFT RESEARCH   (United States)

Author keywords

Codes; Correcting; ECCs; Error; LBCs; TCAMs

Indexed keywords

BIT-ERRORS; CODE-WORDS; CODES; CONTENT ADDRESSABLE MEMORIES; CORRECT ERROR; DATA BITS; ERROR CORRECTING CODE; ERROR MITIGATION; ERROR-RESILIENT; LINEAR BLOCK CODE; MATCH LINE; MEMORY DENSITY; RANDOM ACCESS MEMORIES; SENSE AMPLIFIER; SILICON TECHNOLOGIES; SIMPLE MAJORITY; SOFT ERROR; SOFT-ERROR TOLERANCE; TERNARY CAM; TERNARY CONTENT ADDRESSABLE MEMORIES;

ARTIFICIAL INTELLIGENCE; ASSOCIATIVE STORAGE; BLOCK CODES; CAMS; CONCATENATED CODES; ERROR CORRECTION; INFORMATION THEORY; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; RANDOM ERRORS;

BIT ERROR RATE;

EID: 75449119471     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.179     Document Type: Article

References (5)

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3. N. Azizi and F.N. Najm, "A Family of Cells to Reduce the Soft- Error-Rate in Ternary-Cam," Proc. 43rd Ann. ACM/IEEE Design Automation Conf. (DAC '06), pp. 779-784, 2006.
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5. K. Pagiamtzis and A. Sheikholeslami, "Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey," IEEE J. Solid- State Circuits, vol.41, no.3, pp. 712-727, http://pagiamtzis.com/cam/ camintro.html, Mar. 2006.