A novel architecture for a high-performance network processing unit: Flexibility at multiple levels of abstraction

2009 International Conference on High Performance Switching and Routing, HPSR 2009

Volumn , Issue , 2009, Pages

  Hauger, Simon ^a  

^a UNIVERSITY OF STUTTGART   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURABILITY; FINE GRAINS; HIGH PERFORMANCE NETWORKS; HIGH PROCESSING POWER; HIGH-SPEED; MILLION PACKETS PER SECONDS; MULTIPLE LEVELS; NETWORK PROCESSING; NETWORK PROCESSOR; NEW SERVICES; NOVEL ARCHITECTURE; PARAMETER LEVELS; PROTOTYPICAL IMPLEMENTATION; REGISTER TRANSFER LEVEL;

ABSTRACTING; COMPUTER SOFTWARE; HIGH SPEED NETWORKS; LOGIC GATES; SIGNAL RECEIVERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 74949132918     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPSR.2009.5307421     Document Type: Conference Paper

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