DynaCORE - A dynamically reconfigurable coprocessor architecture for network processors

Proceedings - 14th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2006

Volumn 2006, Issue , 2006, Pages 101-108

  Albrecht, Carsten ^a   Foag, Jürgen ^a,b   Koch, Roman ^a   Maehle, Erik ^a  

^a UNIVERSITY OF LÜBECK   (Germany)

^b ROHDE AND SCHWARZ GMBH AND CO KG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK PROCESSORS; PACKET PROCESSING; PAY LOADPROCESSING; PROGRAMMABLE DEVICES;

DATA PROCESSING; NETWORK PROTOCOLS; PACKET NETWORKS; ROUTERS;

PROGRAM PROCESSORS;

EID: 33750215907     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP.2006.30     Document Type: Conference Paper

References (20)

1. C. Albrecht, R. Hagenau, E. Maehle, A. C. Döring, and A. Herkersdorf. A comparison of parallel programming models of network processors. In PASA 2004, 7th Workshop Parallel Systems and Algorithms, Augsburg, Germany, Lecture Notes in Informatics (LNI), pages 390-399, 2004.
2. M. Baron. Stretching performance. Microprocessor Report, 18(4): 1-5, Apr. 2004.
3. F. Braun, J. Lockwood, and M. Waldvogel. Protocol wrappers for layered network packet processing in reconfigurable hardware. IEEE Micro, 22(3):66-74, Feb. 2002.
4. P. Butel, G. Habay, and A. Rachet. Managing partial dynamic reconfiguration in Virtex-II Pro FPGAs. Xcell Journal, (50):32-37, Aug. 2004. Published by Xilinx, Inc., San Jose, CA.
5. A. C. Döring. Architektur flexibler Router für lokale Hochgeschwindigkeitsnetzwerke, PhD thesis, Institute of Computer Engineering, University of Lübeck, 2002.
6. V. Eck, P. Kalra, R. LeBlanc, and J. McManus. In-Circuit Partial Reconfiguration of RocketIO Attributes. Xilinx, Inc., May 26 2004. Xilinx Application Note 662.
7. J. Foag and R. Koch. Architecture conception of a reconfigurable network coprocessor platform (DynaCORE) for flexible task offloading. In ANCHOR 2004, München, pages 32-38, 2004.
8. J. Foag and R. Koch. Towards a runtime reconfigurable network-on-chip-based network processor. In Applied Reconfigurable Computing 2005 (ARC 2005) Workshop Proceedings, Algarve, Portugal, 2005.
9. R. Hagenau, C. Albrecht, E. Maehle, and A. C. Döring. Parallel processing in network processing architectures, it - Information Technology, 47(3): 123-131, 2005.
10. Hifn Inc. Hifn 5NP4G Network Processor. Fact Sheet, 2004.
11. Intel Corporation. Intel IXP2400 Network Processor. Datasheet, 2004.
12. J. Lockwood, J. Turner, and D. Taylor. Field programmable port extender (FPX) for distributed routing and queuing. In ACM International Symposium on Field Programmable Gate Arrays (FPGA '2000), Monterey, CA, pages 137-144], Feb. 2000.
13. K. Mackenzie, D. Schimmel, S. Yalamanchili, C. Clark, A. Johnson, C. Ulmer, and C. Wood. Active system area networks (ASAN). Poster, Mar. 28 2002.
14. K. Mackenzie, W. Shi, A. McDonald, and I. Ganev. An Intel IXP1200-based network interface. In Workshop on Novel Uses of System Area Networks at HPCA (SAN-2), 2003.
15. N. McKeown. Weren't routers supposed to be simple? ICSI informal talk, May 2002.
16. B. Mei, S. Vernalde, H. De Man, and R. Lauwereins. Design and optimization of dynamically reconfigurable embedded system. In Proc. of International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, NV, pages 25-28, June 2001.
17. V. Pasham and S. Trimberger. High-Speed DES and Triple DES Encryptor/Decryptor. Xilinx, Inc., Aug. 03 2001. Xilinx Application Note 270.
18. C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele. Reconfigurable hardware in wearable computing nodes. In In Proceedings of the 6th International Symposium on Wearable Computers (ISWC), pages 215-222, 2002.
19. D. Taylor, J. Turner, J. Lockwood, and E. Horta. Dynamic hardware plugins (dhp): Exploiting reconfigurable hardware for high-performance programmable routers. Computer Networks, Elsevier Science, 38(3):295-310, Feb. 2002.
20. M. Taylor, J. Kim, J. Miller, et al. The RAW microprocessor: A computational fabric for software circuits and general purpose programs. IEEE Micro, 22(2):25-35, Mar./Apr. 2002.