-
1
-
-
84897581342
-
-
Intel xeon processor. http://www.intel.com/support/processors/xeon/.
-
Intel xeon processor
-
-
-
4
-
-
74049130464
-
-
Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor-White Paper, March 2004.
-
Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor-White Paper, March 2004.
-
-
-
-
6
-
-
27544432558
-
The Impact of Performance Asymmetry in Emerging Multicore Architectures
-
S. Balakrishnan, R. Rajwar, M. Upton, and K. Lai. The Impact of Performance Asymmetry in Emerging Multicore Architectures. In ISCA-32, 2005.
-
(2005)
ISCA-32
-
-
Balakrishnan, S.1
Rajwar, R.2
Upton, M.3
Lai, K.4
-
8
-
-
51549095074
-
The PARSEC Benchmark Suite: Characterization and Architectural Implications
-
Technical Report TR-811-08, Princeton University
-
C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. Technical Report TR-811-08, Princeton University, 2008.
-
(2008)
-
-
Bienia, C.1
Kumar, S.2
Singh, J.P.3
Li, K.4
-
10
-
-
63549151745
-
-
New York, NY, USA, ACM
-
Q. Cai, J. Gonzalez, R. Rakvic, G. Magklis, P. Chaparro, and A. Gonzalez. Meeting points: Using thread criticality to adapt multicore hardware to parallel regions. In PACT '08, New York, NY, USA, 2008. ACM.
-
(2008)
PACT '08, Meeting points: Using thread criticality to adapt multicore hardware to parallel regions
-
-
Cai, Q.1
Gonzalez, J.2
Rakvic, R.3
Magklis, G.4
Chaparro, P.5
Gonzalez, A.6
-
11
-
-
0033242228
-
-
J. W. Demmel, J. R. Gilbert, and X. S. Li. An Asynchronous Parallel Supernodal Algorithm for Sparse Gaussian Elimination. SIAM J. Matrix Analysis and Applications, 20(4):915-952, 1999.
-
J. W. Demmel, J. R. Gilbert, and X. S. Li. An Asynchronous Parallel Supernodal Algorithm for Sparse Gaussian Elimination. SIAM J. Matrix Analysis and Applications, 20(4):915-952, 1999.
-
-
-
-
12
-
-
74049109870
-
-
A. J. Dorta, C. Rodriguez, F. D. Sande, and A. Gonzalez-Ecsribano. The OpenMP Source Code Repository: an Infrastructure to Contribute to the Development of OpenMP
-
A. J. Dorta, C. Rodriguez, F. D. Sande, and A. Gonzalez-Ecsribano. The OpenMP Source Code Repository: an Infrastructure to Contribute to the Development of OpenMP.
-
-
-
-
13
-
-
84878401353
-
Operating System Scheduling On Heterogeneous Core Systems
-
Technical report, Sun Microsystem, 2007
-
A. Fedorova, D. Vengerov, and D. Doucette. Operating System Scheduling On Heterogeneous Core Systems. Technical report, Sun Microsystem, 2007.
-
-
-
Fedorova, A.1
Vengerov, D.2
Doucette, D.3
-
14
-
-
33847168223
-
Power-Performance Efficiency of Asymmetric Multiprocessors for Multi-threaded Scientific Applications
-
R. Grant and A. Afsahi. Power-Performance Efficiency of Asymmetric Multiprocessors for Multi-threaded Scientific Applications. In IPDPS, 2006.
-
(2006)
IPDPS
-
-
Grant, R.1
Afsahi, A.2
-
16
-
-
4644370318
-
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
-
R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas. Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. In ISCA-31, 2004.
-
(2004)
ISCA-31
-
-
Kumar, R.1
Tullsen, D.M.2
Ranganathan, P.3
Jouppi, N.P.4
Farkas, K.I.5
-
17
-
-
56749104535
-
Efficient Operating System Scheduling for Performance-Asymmetric Multi-Core Architecture
-
T. Li, D. Baumberger, D. A. Koufaty, and S. Hahn. Efficient Operating System Scheduling for Performance-Asymmetric Multi-Core Architecture. In SC 07, 2007.
-
(2007)
SC 07
-
-
Li, T.1
Baumberger, D.2
Koufaty, D.A.3
Hahn, S.4
-
19
-
-
67650067694
-
Thread Scheduling in FreeBSD 5.2
-
M. K. McKusick and G. V. Neville-Neil. Thread Scheduling in FreeBSD 5.2. Queue, 2(7):58-64, 2004.
-
(2004)
Queue
, vol.2
, Issue.7
, pp. 58-64
-
-
McKusick, M.K.1
Neville-Neil, G.V.2
-
20
-
-
33947328378
-
Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors
-
T. Y. Morad, U. C. Weiser, A. Kolodny, M. Valero, and E. Ayguade. Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors. Computer Architecture Letters, 5(1), 2006.
-
(2006)
Computer Architecture Letters
, vol.5
, Issue.1
-
-
Morad, T.Y.1
Weiser, U.C.2
Kolodny, A.3
Valero, M.4
Ayguade, E.5
-
21
-
-
77956530676
-
Scheduling on Heterogeneous Multicore Processors Using Architectural Signatures
-
D. Shelepov and A. Fedorova. Scheduling on Heterogeneous Multicore Processors Using Architectural Signatures. In WIOSCA, 2008.
-
(2008)
WIOSCA
-
-
Shelepov, D.1
Fedorova, A.2
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