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Volumn 145-146, Issue , 2009, Pages 177-180
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Low temperature pre-epi treatment: Critical parameters to control interface contamination
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Author keywords
Embedded SiGe; Epitaxial growth; HBT; Low thermal budget; Si SiGe
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Indexed keywords
BUDGET CONTROL;
CONTAMINATION;
DEFECTS;
LEAKAGE CURRENTS;
PHOTOLUMINESCENCE;
SECONDARY ION MASS SPECTROMETRY;
SEMICONDUCTOR GROWTH;
SILICON;
SILICON ALLOYS;
EPITAXIAL GROWTH;
HETEROJUNCTION BIPOLAR TRANSISTORS;
TEMPERATURE;
CLEANING METHODS;
CONTAMINATION LEVELS;
CONTROL INTERFACES;
CRITICAL PARAMETER;
DEFECT GENERATION;
DEPOSITION PROCESS;
DEVICE CHARACTERISTICS;
DEVICE GENERATION;
DIODE CHARACTERIZATION;
EPITAXIAL SI;
EX SITU;
FREE SI;
IN-SITU;
LIFETIME MEASUREMENTS;
LOW TEMPERATURES;
LOW THERMAL BUDGET;
PRE-EPI BAKE;
PROCESS EQUIPMENTS;
SECONDARY ION MASS SPECTROSCOPY;
SI/SIGE;
SIGE EPITAXIAL GROWTH;
SIGE LAYERS;
STATE OF THE ART;
THERMAL BUDGET;
WET CHEMICALS;
EMBEDDED SIGE;
SEMICONDUCTING SILICON COMPOUNDS;
SI-GE ALLOYS;
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EID: 73649101723
PISSN: 10120394
EISSN: None
Source Type: Book Series
DOI: 10.4028/www.scientific.net/SSP.145-146.177 Document Type: Conference Paper |
Times cited : (27)
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References (15)
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