메뉴 건너뛰기




Volumn , Issue , 2009, Pages 392-395

A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK GENERATOR; CMOS TECHNOLOGY; FREQUENCY-LOCKED-LOOP; LINE REGULATION; MEMS OSCILLATORS; ON-CHIP REFERENCES; POWER DISSIPATION; QUARTZ RESONATORS; REFERENCE GENERATOR; TEMPERATURE COEFFICIENT; WIDE FREQUENCY RANGE;

EID: 72849135406     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2009.5325940     Document Type: Conference Paper
Times cited : (40)

References (8)
  • 3
    • 31644444370 scopus 로고    scopus 로고
    • Process and Temperature Compensation in a 7-MHz CMOS Clock Oscillator
    • K. Sundaresan, P. E. Allen, F. Ayazi, "Process and Temperature Compensation in a 7-MHz CMOS Clock Oscillator," IEEE Journal of Solid-State Circuits, vol. 41, no, 2, pp. 433-442, 2006.
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.2 , pp. 433-442
    • Sundaresan, K.1    Allen, P.E.2    Ayazi, F.3
  • 5
    • 70349280605 scopus 로고    scopus 로고
    • A Precision Relaxation Oscillator with a Self-Clocked Offset-Cancellation Scheme for Implantable Biomedical SoCs
    • K. Choe, O. D. Bernal, D. Nuttman, M. Je, "A Precision Relaxation Oscillator with a Self-Clocked Offset-Cancellation Scheme for Implantable Biomedical SoCs," ISSCC Dig. Tech. Papers, pp. 402-403, 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 402-403
    • Choe, K.1    Bernal, O.D.2    Nuttman, D.3    Je, M.4
  • 6
    • 70349291212 scopus 로고    scopus 로고
    • An On-chip CMOS Relaxation Oscillator with Power Averaging Feedback Using a Reference Proportional to Supply Voltage
    • Y. Tokunaga, S. Sakiyama, A. Matsumoto, S. Dosho, "An On-chip CMOS Relaxation Oscillator with Power Averaging Feedback Using a Reference Proportional to Supply Voltage," ISSCC Dig. Tech. Papers, pp. 404-405, 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 404-405
    • Tokunaga, Y.1    Sakiyama, S.2    Matsumoto, A.3    Dosho, S.4
  • 8
    • 25144514874 scopus 로고    scopus 로고
    • Modeling and sizing for minimum energy operation in subthreshold circuits
    • B.H. Calhoun, A. Wang, A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE J. Solid-State Circuits, vol. 40, no.9, pp. 1778-1786, 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.9 , pp. 1778-1786
    • Calhoun, B.H.1    Wang, A.2    Chandrakasan, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.