A 125 GOPS 583 mW network-on-chip based parallel processor with bio-inspired visual attention engine

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 136-147

  Kim, Kwanho ^a   Lee, Seungjin ^a   Kim, Joo Young ^a   Kim, Minsu ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Matching accelerator; Network on chip (NoC); Object recognition; Parallel processor; Processing element clusters; Visual attention engine

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CELLULAR NEURAL NETWORKS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ENERGY MANAGEMENT; IMAGE PROCESSING; NEURAL NETWORKS; PARALLEL ALGORITHMS; SHIFT REGISTERS;

MATCHING ACCELERATOR; NETWORK-ON-CHIP (NOC); PARALLEL PROCESSOR; PROCESSING ELEMENT CLUSTERS; VISUAL ATTENTION ENGINE;

OBJECT RECOGNITION;

EID: 58149234155     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2007157     Document Type: Conference Paper

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