Self-optimization of MPSoCs targeting resource efficiency and fault tolerance

Proceedings - 2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2009

Volumn , Issue , 2009, Pages 467-473

  Porrmann, Mario ^a   Purnaprajna, Madhura ^a   Puttmann, Christoph ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED RISC PROCESSORS; HIERARCHICAL NETWORK; MINIMAL AREA; ON-CHIP MULTIPROCESSOR; PROPOSED ARCHITECTURES; RE-CONFIGURABLE; RECONFIGURABILITY; RESOURCE EFFICIENCIES; RUNTIMES; SCALABLE ARCHITECTURES; SELF-OPTIMIZATION; SELF-OPTIMIZING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; QUALITY ASSURANCE;

COMPUTER ARCHITECTURE;

EID: 72849113628     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2009.52     Document Type: Conference Paper

References (15)

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