Efficient service allocation in hardware using credit-controlled static-priority arbitration

Proceedings - 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009

Volumn , Issue , 2009, Pages 59-68

  Akesson, Benny ^a   Steffens, Liesbeth ^b   Goossens, Kees ^b,c  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Arbitration; CCSP; Implementation; Over allocation; Real time; SoC

Indexed keywords

ALLOCATION STRATEGY; EXPONENTIAL REDUCTION; FINITE PRECISION; HARDWARE IMPLEMENTATIONS; HIGH LOAD; MEMORY CHANNELS; SHARED RESOURCES; SYSTEMS-ON-CHIP; TIGHT BOUND;

COMPUTER SCIENCE; COST REDUCTION; EMBEDDED SYSTEMS; FINITE AUTOMATA; HARDWARE; PROGRAMMABLE LOGIC CONTROLLERS; SCHEDULING;

REAL TIME SYSTEMS;

EID: 72349086587     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTCSA.2009.13     Document Type: Conference Paper

References (26)

1. P. Kollig et al., "Heterogeneous Multi-Core Platform for Consumer Multimedia Applications," in Proc. DATE, 2009.
2. L. Abeni and G. Buttazzo, "Resource Reservation in Dynamic RealTime Systems," Real-Time Systems, vol. 27, no. 2, 2004.
3. K. Goossens et al., "Interconnect and memory organization in SOCs for advanced set-top boxes and TV - Evolution, analysis, and trends," in Interconnect-Centric Design for Advanced SoC and NoC. Kluwer, 2004, ch. 15.
4. B. Akesson et al., "Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration," in Proc. RTCSA, Aug. 2008.
5. G. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications. Springer, 2004.
6. B. Sprunt et al., "Aperiodic task scheduling for Hard-Real-Time systems," Real-Time Systems, vol. 1, no. 1, 1989.
7. J. Rexford et al., "A router architecture for real-time point-to-point networks," in Proc. ISCA, 1996.
8. M. Katevenis et al., "Weighted round-robin cell multiplexing in a general-purpose ATM switch chip," IEEE J. Sel. Areas Commun., vol. 9, no. 8, Oct. 1991.
9. M. Shreedhar and G. Varghese, "Efficient fair queueing using deficit round robin," in Proc. SIGCOMM, 1995.
10. J. Strosnider et al., "The Deferrable Server Algorithm for Enhanced Aperiodic Responsiveness in Hard Real-Time Environments," IEEE Trans. Comput., 1995.
11. H. Zhang, "Service disciplines for guaranteed performance service in packet-switching networks," Proceedings of the IEEE, vol. 83, no. 10, Oct. 1995.
12. C. R. Kalmanek and H. Kanakia, "Rate controlled servers for very highspeed networks," Proc. GLOBECOM, 1990.
13. S. S. Kanhere and H. Sethu, "Fair, efficient and low-latency packet scheduling using nested deficit round robin," High Performance Switching and Routing, 2001 IEEE Workshop on, 2001.
14. D. Saha et al., "Carry-over round robin: a simple cell scheduling mechanism for ATM networks," IEEE/ACM Trans. Netw., vol. 6, no. 6, 1998.
15. S. Hosseini-Khayat and A. Bovopoulos, "A simple and efficient bus management scheme that supports continuous streams," ACM TOCS, vol. 13, no. 2, 1995.
16. T. Bjerregaard and J. Sparsø, "A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip." in ASYNC, 2005.
17. S. Heithecker and R. Ernst, "Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements," in Proc. DAC, 2005.
18. F. Harmsze et al., "Memory arbitration and cache management in stream-based systems," in Proc. DATE, 2000.
19. C. Otero Pérez et al., "Resource reservations in shared-memory multiprocessor SOCs," in Dynamic and Robust Streaming In And Between Connected Consumer-Electronics Devices. Springer, 2005.
20. R. Cruz, "A calculus for network delay. I. Network elements in isolation," IEEE Trans. Inf. Theory, vol. 37, no. 1, 1991.
21. L. Steffens et al., "Real-time analysis for memory access in media processing socs: A practical approach," Proc. ECRTS, 2008.
22. B. Akesson et al., "Real-Time Scheduling of Hybrid Systems using Credit-Controlled Static-Priority Arbitration," NXP Semiconductors, Tech. Rep., 2007, http://www.es.ele.tue.nl/~kakesson/publications/pdf/NXP-TN- 2007-00119.pdf.
23. D. Stiliadis and A. Varma, "Latency-rate servers: a general model for analysis of traffic scheduling algorithms," IEEE/ACM Trans. Netw., vol. 6, no. 5, 1998.
24. B. Akesson et al., "Predator: a predictable SDRAM memory controller," in Proc. CODES+ISSS, 2007.
25. K. Goossens et al., "The æthereal network on chip: Concepts, architectures, and implementations," IEEE Des. Test. Comput., vol. 22, no. 5, Sep. 2005.
26. N. Audsley, "Optimal priority assignment and feasibility of static priority tasks with arbitrary start times," Real-Time Systems, 1991.