A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 210-211

  Wu, Shien Yang ^a   Liaw, J J ^a   Lin, C Y ^a   Chiang, M C ^a   Yang, C K ^a   Cheng, J Y ^a   Tsai, M H ^a   Liu, M Y ^a   Wu, P H ^a   Chang, C H ^a   Hu, L C ^a   Lin, C I ^a   Chen, H F ^a   Chang, S Y ^a   Wang, S H ^a   Tong, P Y ^a   Hsieh, Y L ^a   Pan, K H ^a   Hsieh, C H ^a   Chen, C H ^a   Yao, C H ^a   Chen, C C ^a   Lee, T L ^a   Chang, C W ^a   Lin, H J ^a   Chen, S C ^a   Shieh, J H ^a   Jang, S M ^a   Chen, K S ^a   Ku, Y ^a   See, Y C ^a   Lo, W J ^a   more..

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

1/F NOISE; 32-NM NODE; 45NM TECHNOLOGY; ACTIVE POWER; GATE DENSITY; GATE OXIDE PROCESS; HIGH DENSITY; LOW OPERATING POWER; LOW POWER; LOW POWER TECHNOLOGIES; LOW POWER TRANSISTORS; METAL LAYER; PLATFORM TECHNOLOGY; Q-FACTORS; SCALING TRENDS; SPEED IMPROVEMENT; SRAM CELL; TEST-CHIP; UNIT CAPACITANCE;

GATES (TRANSISTOR); NANOTECHNOLOGY; POWER ELECTRONICS; STATIC RANDOM ACCESS STORAGE;

TECHNOLOGY;

EID: 71049135709     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. S.Y. Wu et al., Proc. IEDM Tech. Dig., pp. 263-266, 2007.
2. X. Chen et al., Symp. VLSI Tech. Dig., pp. 88-89, 2008.
3. F. Arnaud et al., Proc. IEDM Tech. Dig., pp. 633-636, 2008.
4. S. Natarajan et al., Proc. IEDM Tech. Dig., pp. 941-943, 2008.