Adding mechanisms for QoS to a network-on-chip

Proceedings of the 22nd Symposium on Integrated Circuits and Systems Design, SBCCI 2009

Volumn , Issue , 2009, Pages

  Berejuck, Marcelo Daniel ^a   Zeferino, Cesar Albenes ^b  

^a R and D Intelbras SA   (Brazil)

^b UNIVERSIDADE DO VALE DO ITAJAÍ   (Brazil)

Author keywords

FPGA; Networks on chip; Systems on chip

Indexed keywords

BEST EFFORT; BEST EFFORT NETWORKS; CIRCUIT SWITCHING; DIFFERENT MECHANISMS; HIGH DENSITY; INTERCONNECTION ARCHITECTURE; NETWORK ON CHIP; NETWORKS ON CHIPS; QOS REQUIREMENTS; SCALABLE PERFORMANCE; SYSTEMC; SYSTEMS ON CHIPS; VIRTUAL CHANNELS;

COMMUNICATION CHANNELS (INFORMATION THEORY); ELECTRIC NETWORK TOPOLOGY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; NETWORK PERFORMANCE; SYSTEMS ENGINEERING;

MICROPROCESSOR CHIPS;

EID: 70949096563     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1601896.1601928     Document Type: Conference Paper

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