Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Buchanan, Keith ^a   Burgess, Stephen ^a   Giles, Kathrine ^a   Muggeridge, Matthew ^a   Zhao, Hao ^a  

^a Aviza Technologies   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CONFORMALITY; DIELECTRIC LINERS; ETCH PROCESS; LOW LEAKAGE; LOW TEMPERATURE PROCESSING; LOW TEMPERATURES; METALLIZATIONS; SIDEWALL ROUGHNESS; THROUGH SILICON VIAS;

ASPECT RATIO; DIELECTRIC MATERIALS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION;

THREE DIMENSIONAL;

EID: 70549103314     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306552     Document Type: Conference Paper

References (5)

1. S. Arkalgud, 'The promise of through silicon vias' DATE 2009 Workshop on 3D integration, Nice, France, 24 April 2009 (electronic proceedings)
2. K. Takahashi, K. Sekiguchi, 'Through silicon via and 3-D wafer/chip stacking technology, VLSI Circuits, 2006, Digest of technical papers, 2006 Symposium, pp88-92, Honolulu HI
3. N.Urbansky, S.R Burgess, S. Schmidbauer, U. Heydenreich, H. Donohue, I. Moncrieff et al, 'Advanced Hi-Fill for interconnect liner applications, J. Microelectronic Engineering 64 (2002) pp99-105
4. N. Ranganathan, K. Prasad, N. Balasubramanian and K. L. Pey, 'A study of thermo-mechanical stress and its impact on throughsilicon vias'. J. Micromech. Microeng. Issue 7, July 2008.
5. 'Handbook of multilevel metallization for integrated circuits', Edited by S.R. Wilson, C.J. Tracey and J. L Freeman, Noyes Publications 1993, pp246-247