A low-power, fast acquisition, data recovery circuit with digital threshold decision for SFI-5 application

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 12, 2009, Pages 1742-1748

  Du, Qingjin ^a   Zhuang, Jingcheng ^b   Kwasniewski, Tad ^c  

^a TEXAS INSTRUMENTS   (United States)

^b Carleton University ^*

^c CARLETON UNIVERSITY   (Canada)

Author keywords

Clock and data recovery (CDR); Digital threshold; Examining window; Jitter tolerance; Phase locked loop (PLL)

Indexed keywords

CLOCKS; JITTER; LOW POWER ELECTRONICS; PHASE LOCKED LOOPS; RECOVERY; TIMING CIRCUITS;

CLOCK AND DATA RECOVERY; DATA RECOVERY CIRCUITS; DIGITAL THRESHOLD; FAST ACQUISITION; JITTER TOLERANCE; MEASURED RESULTS; PHASE LOCKED LOOP (PLL); UPDATING TECHNIQUES;

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS);

EID: 70549088000     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2017794     Document Type: Article

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