Limited early value communication to improve performance of transactional memory

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2009, Pages 421-429

  Pant, Salil ^a   Byrd, Gregory T ^a  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

B.3.2 memory systems : design styles; C.1.4 processor architectures : parallel architectures; Design; Performance

Indexed keywords

COHERENCE PROTOCOL; CPU ARCHITECTURE; DATA-FORWARDING; DESIGN PERFORMANCE; DESIGN STYLES; EARLY VALUE; MEMORY SYSTEMS; MULTI CORE; PROCESSOR ARCHITECTURES; TRANSACTIONAL MEMORY; VALUE PREDICTION;

DESIGN; INTELLIGENT CONTROL; PARALLEL ARCHITECTURES; PARALLEL PROGRAMMING; STORAGE ALLOCATION (COMPUTER);

NETWORK ARCHITECTURE;

EID: 70449713893     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1542275.1542334     Document Type: Conference Paper

References (17)

1. C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie. Unbounded transactional memory. IEEE Micro, 26(1):59-69, 2006.
2. Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, and David A. Wood. Performance pathologies in hardware transactional memory. SIGARCH Comput. Archit. News, 35(2):81-91, 2007.
3. Lance Hammond, Brian D. Carlstrom, Vicky Wong, Michael Chen, Christos Kozyrakis, and Kunle Olukotun. Transactional coherence and consistency: Simplifying parallel hardware and software. IEEE Micro, 24(6):92-103, 2004.
4. M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural Support For Lock-Free Data Structures. In Proceedings of theTwentieth Annual International Symposium on Computer Architecture, 1993.
5. Maurice Herlihy, Victor Luchango, Mark Moir, and III William N. Scherer. Software transactional memory for dynamic-sized data structures. pages 92-101, Jul 2003.
6. A. Kagi, D. Burger, and J.R. Goodman. Efficient Synchronization: Let them eat QOLB. Computer Architecture, 1997. Conference Proceedings. The 24th Annual International Symposium on, pages 170-180, 2-4 Jun 1997.
7. Sanjeev Kumar, Michael Chu, Christopher J. Hughes, Partha Kundu, and Anthony Nguyen. Hybrid transactional memory. In Proceedings of Symposium on Principles and Practice of Parallel Programming, Mar 2006.
8. Peter S. Magnusson, Magnus Christensson, Jesper Eskilson, Daniel Forsgren, Gustav Hallberg, Johan Hogberg, Fredrik Larsson, Andreas Moestedt, and Bengt Werner. Simics: A full system simulation platform. Computer, 35(2):50-58, 2002.
9. Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood. Multifacet's general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Comput. Archit. News, 33(4):92-99, 2005.
10. John M. Mellor-Crummey and Michael L. Scott. Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Trans. Comput. Syst., 9(1):21-65, 1991.
11. Chi Cao Minh, JaeWoong Chung, Christos Kozyrakis, and Kunle Olukotun. Stamp: Stanford transactional applications for multi-processing. In Proceedings of The IEEE International Symposium on Workload Characterization, Sep 2008.
12. K.E. Moore, J. Bobba, M.J. Moravan, M.D. Hill, and D.A. Wood. Logtm: log-based transactional memory. High-Performance Computer Architecture, 2006. The Twelfth International Symposium on, pages 254-265, 11-15 Feb. 2006.
13. Salil Pant and Gregory Byrd. Extending Concurrency of Transactional Memory Programs by using Value Prediction. Accepted for publication at Computing Frontiers '09.
14. R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. pages 494-505, 2005.
15. Ravi Rajwar and James R. Goodman. Transactional lock-free execution of lock-based programs. SIGPLAN Not., 37(10):5-17, 2002.
16. Hany E. Ramadan, Christopher J. Rossbach, and Emmett Witchel. Dependence-aware transactional memory for increased concurrency. In MICRO '08: Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, pages 246-257, Washington, DC, USA, 2008. IEEE Computer Society.
17. Sun Microsystems. UltraSPARC III Cu User's manual, 2004. Version 2.2.1.