Hardware support for bulk data movement in server platforms

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 53-60

  Zhao, Li ^a   Iyer, Ravi ^b   Makineni, Srihari ^b   Bhuyan, Laxmi ^a   Newell, Don ^b  

^a University of California Riverside   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPY ENGINE ARCHITECTURE; DATA MOVEMENT; SERVER PLATFORMS;

COMPUTER ARCHITECTURE; DATA PROCESSING; HARDWARE; MICROPROCESSOR CHIPS; SEARCH ENGINES;

SERVERS;

EID: 33748543231     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.64     Document Type: Conference Paper

References (16)

1. G. Regnier, S. Makineni, R. Illikkal, R. Iyer, and et al., "TCP onloading for datacenter servers," IEEE Computer Magazine, November 2004.
2. S. Makineni and R. Iyer, "Performance characterization of TCP/IP processing in commercial server work-loads," in 6th IEEE Workshop on Workload Characterization (WWC-6), October 2003.
3. J. L. Hennessy and D. A. Patterson, Computer Architecture A Quantitative Approach. Morgan Kaufmann Publishing Company, 1999.
4. D. Marr and et al., "Hyper-threading technology architecture and microarchitecture," Intel Technology Journal, February 2002.
5. D. Tullsen, S. Eggers, and H. Levy, "Simultaneous multithreading: Maximizing on-chip parallelism," in Proc. of the 22nd Annual International Symposium on Computer Architecture June 1995, pp. 392-403.
6. D. Callahan and et al., "Software prefetching," in 4th Int'l conference on Architectural support for programming languages and operating systems, April 1991.
7. T. Chen, "An effective programmable prefetch engine for on-chip caches," in Micro-28, December 1995.
8. Intel Corporation, "IA-32 intel architecture optimization reference manual." [Online], Available: http://www.intel.com/design/Pentium4/ documentation.htm
9. _, "Pentium(R) Pro family developer's manual, volume 1: Specifications." [On-line]. Available: http://developer.intel.com/design/ archives/processors/pro/docs/242690.htm
10. D. Burger and T. Austin, "The SimpleScalar Tool Set, version 2.0," University of Wisconsin, Tech. Rep. CS-TR-97-1342, June 1997.
11. M. K. McKusick and et al., The Design and Implementation of the 4.4BSD Unix Operating System. Addison-Wesley Publishing Company, 1996.
12. J. Brustoloni, "Interoperation of copy avoidance in network and file I/O," in IEEE INFOCOM, March 1999.
13. J. Brustoloni and P. Steenkiste, "Effects of buffering semantics on I/O performance," in Proc. OSDI-II, USENIX, October 1996, pp. 277-291.
14. M. Thadani and Y. Khalidi, "An efficient zero-copy I/O framework for UNIX," Sun Microsystems Laboratories, Tech. Rep. SMLITR-95-39, May 1995.
15. RDMA Consortium, "Architectural specifications for RDMA over TCP/IP." [Online]. Available: http://www.rdmaconsortium.org
16. Sun Microsystems Laboratories, "Accelerating core networking functions using the UltraSPARC VIS[tm] instruction set." [Online]. Available: http://www.sun.com